1. Field of the Invention
The present invention relates to a direct memory access controller, specifically to a direct memory access controller which controls the direct memory access between internal modules and high speed external memories such as SDRAM(Synchronous Dynamic RAM) in high speed digital signal processors having burst transmission feature.
2. Description of the Prior Art
Referring to FIG. 1a and FIG. 1b, the prior art direct memory access scheme of multimedia processors having parallel processing structure using a plurality of processing modules and high speed external memories such as SDRAM for image compression/decompression will be explained.
FIG. 1a is a diagram of the prior art fly-by type direct memory access control scheme which is used in IBM compatible computers. In the fly-by type scheme, the direct memory access controller 1 applies address and control signal to the target memory 3 and at the same time sends control signals to the input/output device 2. The input/output device 2 has an input/output structure which complies to the direct memory access request signal 5 and the direct memory access response signal 6 and in which the address signal is ignored.
FIG. 1b is a diagram of the prior art flow-through type direct memory access scheme which is used in Intel 80186 processors. In the flow-through type scheme, the direct memory access controller has the same interface as that of the general CPU, and uses two input/output actions, i.e. writing the data from the read action is stored in a temporary memory 4 in the direct memory access controller 1, and then write action is performed to transmit data.
In the fly-by type scheme, there is no delay in burst transmission because data is transmitted while the memory 1 and the input/output device 2 is connected directly. But, an additional interface for direct memory access transmission in the input/output device 2 is required.
The flow-through type has a simple interface but requires twice of transmission cycles compared to the fly-by type. Further, it requires a temporary memory as long as the length of the burst to be connected to the burst memories like SDRAM which is operated at the same speed as the system bus.